
module OutputInterface
#(
    parameter oWIDTH = 10,
    parameter iWIDTH = 32,
    parameter oMAX = 10'b01_1111_1111,
    parameter oMIN = 10'b10_0000_0000
)
(
    input wire signed   [iWIDTH-1:0]    i_IntSig,   //Internal Signal
    input wire                          i_clk,      //Sync Clock
    input wire                          i_rst,      //Rst
    input wire                          i_mode,     //0:Direct Output,1:Saturated Output
    output reg signed  [oWIDTH-1:0]    o_ExtSig    //External Signal
);
//added
reg signed [oWIDTH-1:0] SigOut;
wire signed [iWIDTH-1:0] MaxValue;
wire signed [iWIDTH-1:0] MinValue;

assign MaxValue={{(iWIDTH-oWIDTH){oMAX[oWIDTH-1]}},oMAX[oWIDTH-1:0]};
assign MinValue={{(iWIDTH-oWIDTH){oMIN[oWIDTH-1]}},oMIN[oWIDTH-1:0]};

always@(*) begin
    if(i_mode==0) begin
        SigOut=i_IntSig[oWIDTH-1:0];
    end
    else begin
        if(i_IntSig>MaxValue) begin
            SigOut=oMAX;
        end
        else if(i_IntSig<MinValue) begin
            SigOut=oMIN;
        end
        else begin
            SigOut=i_IntSig[oWIDTH-1:0];
        end
    end
end

always@(posedge i_clk or posedge i_rst) begin
    if(i_rst) begin
        o_ExtSig<='b0;
    end
    else begin
        o_ExtSig<=SigOut;
    end
end

endmodule
